A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process

Authors:
Takahito Miyazaki;Masanori Hashimoto;Hidetoshi Onodera
Affiliations:
Kyoto University;Kyoto University;Kyoto University
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

Citing 0
Cited 4

Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
PLL performance comparison with application to spread spectrum clock generator design

Analog Integrated Circuits and Signal Processing
Design and analysis of a second order phase locked loops (PLLs)

TELE-INFO'06 Proceedings of the 5th WSEAS international conference on Telecommunications and informatics
Noise analysis of phase locked loops

TELE-INFO'06 Proceedings of the 5th WSEAS international conference on Telecommunications and informatics

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a performance comparison of two PLLs for clock generation using a ring oscillator based VCO and an LC oscillator based VCO. We fabricate two 1.6GHz PLLs in a 0.18 μm digital CMOS process and compare their performances based on the measurement results. We also predicts major performances of PLLs in the future such as jitter, power consumption and chip area, based on a qualitative evaluation in an analytic way.