Programmable Accelerators for Reconfigurable Video Decoder

  • Authors:

  • Tero Rintaluoma;Timo Reinikka;Joona Rouvinen;Jani Boutellier;Pekka Jääskeläinen;Olli Silvén

  • Affiliations:

  • On2 Technologies, Oulu, Finland;Department of Electrical and Information Engineering, University of Oulu, Finland;Valmet Automotive, Uusikaupunki, Finland;Department of Electrical and Information Engineering, University of Oulu, Finland;Tampere University of Technology, Tampere, Finland;Department of Electrical and Information Engineering, University of Oulu, Finland

  • Venue:
  • SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

Practically all modern video coding standards such as H.264, MPEG-4 and VC-1 are based on hybrid transform based block motion compensated techniques, that employ almost the same coding tools. The same approach is used with numerous non-standard proprietary codecs, with decoders available via Internet as browser plugins. For mobile devices power efficient hardware accelerators have been developed, but usually only a few standards are supported. Consequently, the decoding of the other formats, including the non-standard ones is done by software, sacrificing the battery life. In this paper we present programmable accelerators for arithmetic code decoding and motion compensation, that can be used with multiple video standards. These functions consume more than half of the cycles in software based decoders. Although the accelerators were originally designed for H.264 standard, they are rather generic for the respective coding tools. They have been implemented on application specific processor technology for flexibility and energy efficiency with the aim of achieving the performance needed for decoding high definition (1920x1088, 30 fps) video.