Motion compensation hardware accelerator architecture for H.264/AVC

Authors:
Bruno Zatt;Valter Ferreira;Luciano Agostini;Flávio R. Wagner;Altamiro Susin;Sergio Bampi
Affiliations:
Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil;Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil;Informatics Department, Federal University of Pelotas, Pelotas, RS, Brazil;Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil;Electrical Engineering Department, Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil;Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil
Venue:
PSIVT'07 Proceedings of the 2nd Pacific Rim conference on Advances in image and video technology
Year:
2007

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Abstract

This work presents a new hardware acceleration solution for the H.264/AVC motion compensation process. A novel architecture is proposed to precede the luminance interpolation task, which responds by the highest computational complexity in the motion compensator. The accelerator module was integrated into the VHDL description of the MIPS Plasma processor, and its validation was accomplished by simulation. A performance comparison was made between a software implementation and a hardware accelerated one. This comparison indicates a reduction of 94% in processing time. The obtained throughput is enough to reach real time when decoding H.264/AVC Baseline Profile motion compensation for luminance at Level 3.