Parallelized Architecture of Multiple Classifiers for Face Detection

Authors:
Junguk Cho;Bridget Benson;Shahnam Mirzaei;Ryan Kastner
Affiliations:
-;-;-;-
Venue:
ASAP '09 Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
Year:
2009

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Abstract

This paper presents a parallelized architecture of multiple classifiers for face detection based on the Viola and Jones object detection method. This method makes use of the AdaBoost algorithm which identifies a sequence of Haar classifiers that indicate the presence of a face. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing of classifiers, and parallel processing of multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the parallelized architecture which can be scalable for configurable device with variable resources. We implement the proposed architecture in Verilog HDL on a Xilinx Virtex-5 FPGA and show the parallelized architecture of multiple classifiers can have 3.3脳 performance gain over the architecture of a single classifier and an 84脳 performance gain over an equivalent software solution.