A novel hardware architecture for rapid object detection based on adaboost algorithm

Authors:
Tinghui Wang;Feng Zhao;Jiang Wan;Yongxin Zhu
Affiliations:
Digilent Electronic Technology Co. Ltd.;Digilent Electronic Technology Co. Ltd.;Digilent Electronic Technology Co. Ltd.;Shanghai Jiaotong University
Venue:
ISVC'10 Proceedings of the 6th international conference on Advances in visual computing - Volume Part III
Year:
2010

Citing 6
Cited 1

Detecting Faces in Images: A Survey

IEEE Transactions on Pattern Analysis and Machine Intelligence
Robust Real-Time Face Detection

International Journal of Computer Vision
A Parallel Architecture for Hardware Face Detection

ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Parallelized Architecture of Multiple Classifiers for Face Detection

ASAP '09 Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
Partially parallel architecture for AdaBoost-based detection with Haar-like features

IEEE Transactions on Circuits and Systems for Video Technology
Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

Face detection system for SVGA source with hecto-scale frame rate on FPGA board

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposed a novel hardware architecture for rapid object detection based on Adaboost learning algorithm with Haar-like features as weak classifiers. A 24×24 pipelined integral image array is introduced to reduce calculation time and eliminate the problem of the huge hardware resource consumption in integral image calculation and storage. An expansion of the integral image array is also proposed to increase the parallelism at a low cost of hardware resource consumption. These methods resulted in an optimized detection process. We further implemented the process on Xilinx XUP Virtex II Pro FPGA board, and achieved an accuracy of 91.3%, and a speed of 80 fps at clock rate of 100 MHz, for 352x288 CIF image.