Investigation of transient fault effects in synchronous and asynchronous Network on Chip router
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents a study of fault tolerance behavior of a 32-bit DLX processor. Simulation-based method has been applied to analyze the fault tolerance characteristic of this processor. This experiment is based on injection of 14000 faults among 70 points of components which are more frequently used in VHDL model. The experimental results have been considered in different aspects. Up to 55% of the injected faults cause system failure and also approximately 42% of them are masked before changing into errors. Less than 3% of injected faults remain as latent errors. The Average of fault latency has also been reported between 47 to 59 clock cycles regarding to different workloads. The comparison of observed component distinguishes ALU as the most sensitive one among others with the approximate failure rate of 50%.