Sparse Matrix Operations on Multi-core Architectures

Authors:
Carsten Trinitis;Tilman Küstner;Josef Weidendorfer;Jasmin Smajic
Affiliations:
Lehrstuhl für Rechnertechnik und Rechnerorganisation Institut für Informatik, Technische Universität München, Germany;Lehrstuhl für Rechnertechnik und Rechnerorganisation Institut für Informatik, Technische Universität München, Germany;Lehrstuhl für Rechnertechnik und Rechnerorganisation Institut für Informatik, Technische Universität München, Germany;ABB Corporate Research Center, Baden-Daettwil, Switzerland
Venue:
PaCT '09 Proceedings of the 10th International Conference on Parallel Computing Technologies
Year:
2009

Citing 2
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Abstract

This paper compares various contemporary multi-core based microprocessor architectures with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix operations are used as a benchmark application from the area of electrical engineering. Within this context, thread to core pinnning and cache optimization are two important aspects which are investigated in more detail.