Cache efficiency and scalability on multi-core architectures

Authors:
Thomas Müller;Carsten Trinitis;Jasmin Smajic
Affiliations:
Lehrstuhl für Rechnertechnik und Rechnerorganisation, Institut für Informatik, Technische Universität München, Germany;Lehrstuhl für Rechnertechnik und Rechnerorganisation, Institut für Informatik, Technische Universität München, Germany;ABB Corporate Research Switzerland, Baden, Switzerland
Venue:
PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
Year:
2011

Citing 6
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Abstract

Two electrical engineering applications from industry partners dealing with sparse matrices were analyzed regarding cache efficiency and scalability on modern multi core systems. Two different contemporary multi-core architectures have been investigated, namely Intel's Westmere and AMD's Magny-Cours. This paper can be regarded as a continuation of the investigations presented in [14] and [15]. In addition, the SuiteSparseQR library for efficiently computing QR factorizations of sparse matrices was evaluated regarding scalability and cache efficiency.