Sparse matrix operations on several multi-core architectures

Authors:
Carsten Trinitis;Tilman Küstner;Josef Weidendorfer;Jasmin Smajic
Affiliations:
Lehrstuhl für Rechnertechnik und Rechnerorganisation, Institut für Informatik, Technische Universität München, Munich, Germany;Lehrstuhl für Rechnertechnik und Rechnerorganisation, Institut für Informatik, Technische Universität München, Munich, Germany;Lehrstuhl für Rechnertechnik und Rechnerorganisation, Institut für Informatik, Technische Universität München, Munich, Germany;ABB Corporate Research Center, Baden-Daettwil, Switzerland
Venue:
The Journal of Supercomputing
Year:
2011

Citing 4
Cited 1

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Abstract

This paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products.Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail.