Improved Boosting Algorithms Using Confidence-rated Predictions
Machine Learning - The Eleventh Annual Conference on computational Learning Theory
Detecting Faces in Images: A Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Neural network-based face detection
Neural network-based face detection
Embedded Hardware Face Detection
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Robust Real-Time Face Detection
International Journal of Computer Vision
Vector Boosting for Rotation Invariant Multi-View Face Detection
ICCV '05 Proceedings of the Tenth IEEE International Conference on Computer Vision (ICCV'05) Volume 1 - Volume 01
Joint Haar-like Features for Face Detection
ICCV '05 Proceedings of the Tenth IEEE International Conference on Computer Vision - Volume 2
Face detection for automatic exposure control in handheld camera
ICVS '06 Proceedings of the Fourth IEEE International Conference on Computer Vision Systems
Automatic hardware implementation tool for a discrete Adaboost-based decision algorithm
EURASIP Journal on Applied Signal Processing
Fast rotation invariant multi-view face detection based on real adaboost
FGR' 04 Proceedings of the Sixth IEEE international conference on Automatic face and gesture recognition
Hi-index | 0.00 |
This paper aims at detecting faces with all -/+90-degree rotation-out-of-plane and 360-degree rotation-in-plane pose changes fast and accurately under embedded hardware environment. We present a fine-classified method and a hardware architecture for rotation invariant multi-view face detection. A tree-structured detector hierarchy is designed to organize multiple detector nodes identifying pose ranges of faces. We propose a boosting algorithm for training the detector nodes. The strong classifier in each detector node is composed of multiple novelly-designed two-stage weak classifiers. Each detector node deals with the multi-dimensional binary classification problems by means of a shared output space of multi-components vector. The characteristics of the proposed method is analyzed for fully exploiting the spatial and temporal parallelism. We present the design of the hardware architecture in detail. Experiments on FPGA show that high accuracy and amazing speed are achieved compared with previous related works. The execution time speedups are significant when our FPGA design is compared with software solution on PC.