Using VLSI to reduce serialization and memory traffic in shared memory parallel computers
Proceedings of the fourth MIT conference on Advanced research in VLSI
Continuous Models for Communication Density Constraints on Multiprocessor Performance
IEEE Transactions on Computers
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Cost-bandwidth tradeoffs for communication networks
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Technologies for low latency interconnection switches
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
A Performance Bound of Multistage Combining Networks
IEEE Transactions on Computers
Elementary properties of clock-regulated queues
SIAM Journal on Applied Mathematics
A performance bound analysis of multistage combining networks using a probabilistic model
ICS '91 Proceedings of the 5th international conference on Supercomputing
Issues related to MIMD shared-memory computers: the NYU ultracomputer approach
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Coordinating parallel processors: a partial unification
ACM SIGARCH Computer Architecture News
Architecture and performance of processor-memory interconnection networks for mimd shared memory parallel processing systems
The QRQW PRAM: accounting for contention in parallel algorithms
SODA '94 Proceedings of the fifth annual ACM-SIAM symposium on Discrete algorithms
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