Performance balancing: software-based on-chip memory management for effective CMP executions

  • Authors:

  • Naoto Fukumoto;Kenichi Imazato;Koji Inoue;Kazuaki Murakami

  • Affiliations:

  • Kyushu University, Nishi-ku, Fukuoka City, Japan;Kyushu University, Nishi-ku, Fukuoka City, Japan;Kyushu University, Nishi-ku, Fukuoka City, Japan;Kyushu University, Nishi-ku, Fukuoka City, Japan

  • Venue:
  • Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture
  • Year:
  • 2009

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Abstract

This paper proposes the concept of performance balancing, and reports its performance impact on a Chip multiprocessor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does not scale with the number of cores tends to limit the potential of CMPs. To solve this issue, the technique proposed in this paper attempts to make a good balance between computation and memorization. Unlike conventional parallel executions, this approach exploits some cores to improve the memory performance. These cores devote the on-chip memory hardware resources to the remaining cores executing the parallelized threads. In our evaluation, it is observed that our approach can achieve 31% of performance improvement compared to a conventional parallel execution model in the specified program.