Communicating sequential processes
Communicating sequential processes
Proceedings of the Fourth Annual Symposium on Logic in computer science
In transition from global to modular temporal reasoning about programs
Logics and models of concurrent systems
A model of Ada programs for static deadlock detection in polynomial times
PADD '91 Proceedings of the 1991 ACM/ONR workshop on Parallel and distributed debugging
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Evaluating Deadlock Detection Methods for Concurrent Software
IEEE Transactions on Software Engineering
Compositional State Space Generation from Lotos Programs
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SHIM: a deterministic model for heterogeneous embedded systems
Proceedings of the 5th ACM international conference on Embedded software
Scheduling-independent threads and exceptions in SHIM
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
Assume-Guarantee Reasoning for Deadlock
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Static elaboration of recursion for concurrent software
PEPM '08 Proceedings of the 2008 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation
Breaking up is hard to do: An evaluation of automated assume-guarantee reasoning
ACM Transactions on Software Engineering and Methodology (TOSEM)
Automatic symbolic compositional verification by learning assumptions
Formal Methods in System Design
Learning assumptions for compositional verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Concurrency and Communication: Lessons from the SHIM Project
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
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Concurrent programming languages are growing in importance with the advent of multi-core systems. However, concurrent programs suffer from problems, such as data races and deadlock, absent from sequential programs. Unfortunately, traditional race and deadlock detection techniques fail on both large programs and small programs with complex behaviors. In this paper, we present a compositional deadlock detection technique for a concurrent language--SHIM--in which tasks run asynchronously and communicate using synchronous CSP-style rendezvous. Although SHIM guarantees the absence of data races, a SHIM program may still deadlock if the communication protocol is violated. Our previous work used NuSMV, a symbolic model checker, to detect deadlock in a SHIM program, but it did not scale well with the size of the problem. In this work, we take an incremental, divide-and-conquer approach to deadlock detection. In practice, we find our procedure is faster and uses less memory than the existing technique, especially on large programs, making our algorithm a practical part of the compilation chain.