Design of flash-based DBMS: an in-page logging approach
Proceedings of the 2007 ACM SIGMOD international conference on Management of data
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Hybrid solid-state disks: combining heterogeneous NAND flash in large SSDs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
FRA: a flash-aware redundancy array of flash storage devices
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Write activity reduction on flash main memory via smart victim cache
Proceedings of the 20th symposium on Great lakes symposium on VLSI
LINK-GC: a preemptive approach for garbage collection in NAND flash storages
Proceedings of the 28th Annual ACM Symposium on Applied Computing
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The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to properties such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can increase performance by up to 4 times and durability by 4 times by adding only a small hardware cost.