Full System Simulation and Verification Framework

Authors:
Jing-Wun Lin;Chen-Chieh Wang;Chin-Yao Chang;Chung-Ho Chen;Kuen-Jong Lee;Yuan-Hua Chu;Jen-Chieh Yeh;Ying-Chuan Hsiao
Affiliations:
-;-;-;-;-;-;-;-
Venue:
IAS '09 Proceedings of the 2009 Fifth International Conference on Information Assurance and Security - Volume 01
Year:
2009

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On the interfacing between QEMU and SystemC for virtual platform construction: Using DMA as a case

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.