Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
ACM Transactions on Architecture and Code Optimization (TACO)
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In the multilevel (ML) storage approach, any single cell in a memory array is programmed to one among n2 predetermined different states. To exploit the ML approach in the case of phase change memories (PCMs), it is necessary to accurately program the active chalcogenide layer to a number of different partially crystallized states so as to precisely allocate the electrical resistance of the cell in the range from the maximum to the minimum available value. In this paper, we experimentally investigate the characteristics of two voltage-driven programming algorithms, namely, the single-pulse and the (multi-pulse) staircase-up (SCU) programming algorithm, from a ML storage point of view. To this end, we analyze the impact of the amplitude and the time length of applied voltage pulses on the programmed resistance, showingthat the SCU algorithm appears to be a promising candidate for PCM ML storage.