High speed, high resolution and low power approaches for SAR A/D converter
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
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Through the research on charge redistribution SAR A/D converter, three energy-efficient capacitor arrays are discussed in this paper. The switching energy of the traditional architecture, charge sharing architecture, capacitor splitting architecture and two-step architecture capacitor arrays is derived and analyzed. Based on SMIC 65nm CMOS process, 10-bit SAR A/D converters of all these architectures are designed to validate these concepts. The energy dissipation from Hspice simulation is discussed. At the smallest output code, charge sharing architecture and capacitor splitting architecture consume respectively 65.5% and 44.8% of the energy conventional architecture dissipates. At the smallest and largest output codes, two-step architecture just consumes respectively 10.4% and 23.1% of the traditional architecture’s dissipation.