Thin locks: featherweight synchronization for Java
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors
ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
Chameleon: Application-Level Power Management
IEEE Transactions on Mobile Computing
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A server application running on a chip multiprocessor with many hardware threads often requires extra processor speed (and energy) because of lock contention. We show that boosting the processor speed for frequently contended critical sections in a Java VM can save more energy on a DVFS-enabled server.