Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors

  • Authors:
  • Jian Li;J. F. Martinez

  • Affiliations:
  • -;-

  • Venue:
  • ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
  • Year:
  • 2005

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Abstract