High speed switching for ATM: the BSS
Computer Networks and ISDN Systems
A flexible shared-buffer switch for ATM at Gb/s rates
Computer Networks and ISDN Systems
The Helix switch: a single chip cell switch design
Computer Networks and ISDN Systems
Design and analysis of the stacked-Banyan ATM switch fabric
Computer Networks: The International Journal of Computer and Telecommunications Networking
IEEE Journal on Selected Areas in Communications
The Tera project: a hybrid queueing ATM switch architecture for LAN
IEEE Journal on Selected Areas in Communications
ATM shared-memory switching architectures
IEEE Network: The Magazine of Global Internetworking
A very large-scale switching system by using nested ring-based architecture
Computers and Electrical Engineering
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In order to make data exchange speed fast enough for supporting the current communication systems or networks, a high speed switching system with low transmission delay and low data loss is required. Many researchers used statistical time division multiplexing techniques to design the switching system for achieving a higher throughput. In such switching systems with n input/output ports, the internal execution speed must be n times faster than the speed of the system with single input/output port. This designing philosophy is really not an appropriate way as the demand trend for higher speed system in the future. For improving the drawbacks of the switching system mentioned above, a novel, revolutionary architecture of a Parallel Input Parallel Output Register Switching System (PIPORS) is proposed in this paper. The PIPORS is based on the interconnection of the small distributed Shared Memory Modules (SMM) and the Shift Register Switch Array (SRSA). This construction will accelerate the switching speed. In addition, the number of input/output ports of the system can easily be extended for providing a higher capacity to respond to the trend of fast increasing amount of data transferred in the system. Three simple methods to extend the input/output ports and the capacity of the internal memory are presented. For evaluating the performance of the proposed system, we made some performance comparisons among our PIPORS and Central Shared Memory Switching System (CSMS) with respect to the amount of total memory required, data loss probability, transmission delay and switching performance. It shows that a better performance can be achieved in our PIPORS.