Tunable linear MOS resistors using quasi-floating-gate techniques

  • Authors:
  • A. Torralba;C. Luján-Martínez;Roman G. Carvajal;J. Galan;Melita Pennisi;J. Ramírez-Angulo;A. López-Martín

  • Affiliations:
  • Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, Spain;Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, Spain;Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, Spain;Departamento de Ingeniería Electrónica, de Sistemas Informáticos y Automática, Universidad de Huelva, Spain;Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, University of Catania, Italy;KIipsch School of Electrical Engineering, New Mexico State University, Las Cruces, NM;Departamento de Ingeniería Eléctrica y Electrónica, Universidad Pública de Navarra, Pamplona, Spain

  • Venue:
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • Year:
  • 2009

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Abstract

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor α ≤ 1 is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of α on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of α (α = 0, 0.5, and 1) in a 0.5 µm CMOS technology) with ±1.65-V supply voltage. Experimental results show (for α =1) a THD of -57 dB (HD2 = -70 dB) at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 µA/V and a power consumption of 3.2 mW.