Construction of low-density parity-check codes for data storage and transmission
Construction of low-density parity-check codes for data storage and transmission
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
Low-density parity-check codes based on finite geometries: a rediscovery and new results
IEEE Transactions on Information Theory
Performance of low-density parity-check codes with linear minimum distance
IEEE Transactions on Information Theory
Construction of Regular and Irregular LDPC Codes: Geometry Decomposition and Masking
IEEE Transactions on Information Theory
Results on Punctured Low-Density Parity-Check Codes and Improved Iterative Decoding Techniques
IEEE Transactions on Information Theory
Low-floor decoders for LDPC codes
IEEE Transactions on Communications
Low-floor detection/decoding of LDPC-coded partial response channels
IEEE Journal on Selected Areas in Communications
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While LDPC codes have been widely acclaimed in recent years for their near-capacity performance, they have not found their way into many important applications. For some cases, this is due to their increased decoding complexity relative to the classical coding techniques. For other cases, this is due to their inability to reach very low bit error rates (e.g., 10-12) at low signal-to-noise ratios (SNRs), a consequence of the error-rate floor phenomenon associated with iterative LDPC decoders. In the present paper, we make strides in the low-floor problem by identifying the weaknesses of the code under study and applying compensatory counter-measures. These countermeasures include: modifying the code itself, modifying the decoder, or adding a properly designed outer algebraic code. Our results demonstrate that each of these techniques can successfully lower an LDPC code's floor, and that, for the code under study, an outer BCH code appears to be particularly effective. All of our results are based on FPGA decoder simulations and so they are reliable and repeatable.