Analysis of errors in a comparator-based switched-capacitor biquad filter

Authors:
Randall White;Susan Luschas;Shoba Krishnan
Affiliations:
University of California, Los Angeles, CA and Santa Clara University, Santa Clara, CA;Santa Clara University, Santa Clara, CA;Santa Clara University, Santa Clara, CA
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

Citing 1
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A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors

ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)

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Abstract

Comparator-based switched-capacitor (CBSC) techniques have become popular in reducing power consumption and increasing the speed of data converters. This brief investigates the use of CBSC techniques for implementing a biquad filter. A CBSC implementation of a low-pass biquad is proposed, and the sources of error are analyzed. It is shown that implementing the lossy integrator as the last stage produces a lower offset voltage. The sensitivity of the biquad ω0 and Q to the CBSC overshoot error is shown to be similar to that of the finite operational amplifier gain error in a switched-capacitor filter. Simulation results confirm the presented theory.