Power efficient comparators for long arguments in superscalar processors
Proceedings of the 2003 international symposium on Low power electronics and design
Energy-efficient issue queue design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Isolating Short-Lived Operands for Energy Reduction
IEEE Transactions on Computers
Energy Efficient Comparators for Superscalar Datapaths
IEEE Transactions on Computers
Register file caching for energy efficiency
Proceedings of the 2006 international symposium on Low power electronics and design
A physical level study and optimization of CAM-based checkpointed register alias table
Proceedings of the 13th international symposium on Low power electronics and design
Analysis of errors in a comparator-based switched-capacitor biquad filter
IEEE Transactions on Circuits and Systems II: Express Briefs
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Datapath components in modern high performance superscalar processors employ a significant amount of associative addressing logic based on the use of comparators that dissipate energy on a mismatch. These comparators are used to detect a full match, but as mismatches are much more common than full matches in some components of the CPU,considerable energy-inefficiencies occur within the associative logic. We propose the design of two new comparator circuits that predominantly dissipate energy on a match, thus resulting in very significant savings in comparator power dissipation. The proposed designs are evaluated using SPICE simulations of actual VLSI layouts of the comparators in 0.18 micron 6-metal layer process and micro-architectural level statistics.