Minimum power-consumption estimation in ROM-based DDFS for frequency-hopping ultralow-power transmitters

  • Authors:
  • Emanuele Lopelli;Johan D. Van Der Tang;Arthur H. M. Van Roermund

  • Affiliations:
  • Mixed-Signal Microelectronics Group, Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands and Broadcom Corporation, Bunnik, The Netherlands;Broadcom Corporation, Bunnik, The Netherlands;Mixed-Signal Microelectronics Group, Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands

  • Venue:
  • IEEE Transactions on Circuits and Systems Part I: Regular Papers
  • Year:
  • 2009

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Abstract

The future of all kinds of applications that require a submilliwatt consumption strictly depends on the capability to meet design specifications at the minimum power costs. While several computer-aided-design tools are present to estimate the power consumption of modern ICs at transistor level, it is very difficult to predict the power at higher level. Given the reduced time-to-market of modern communication devices, it is very often needed to have accurate power estimations prior to the transistor-level design. Allocating a too conservative power budget to a block implies a possible poor tradeoff between the specifications of building blocks that constitute the system and their power consumption. For future power-constrained wireless devices (like wireless nodes in sensor networks), it is very important to have high-level models which can help the designer with the initial high-level choices without going into transistor-level design. One of the important blocks in modern communication devices, particularly for spread-spectrum systems, is the frequency synthesizer. In this paper, the first power-consumption model for an ultralow-power ROM-based direct digital frequency synthesizer has been developed, which can help the designer in the power optimization at a high level prior to transistor implementation.