Operation and Modeling of the Mos Transistor (The Oxford Series in Electrical and Computer Engineering)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling R-2R segmented-ladder DACs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Nonlinear R-2R transistor-only DAC
IEEE Transactions on Circuits and Systems Part I: Regular Papers
| Hi-index | 0.00 |
Many recent applications are based on DSPs interfaced to analog I/Os with data converters. In this context, high-performance DACs have become crucial building blocks. The current-steering-flash DAC architecture is the most popular architecture for speed demanding applications. Although limited by component mismatches, resolution of these converters is typically enhanced by calibration solutions such as laser trimming or corrective active circuitry. Dynamic performances, on the other hand, are strongly dependent on switch design and operation which can easily spoil even the best static accuracy level at higher speeds. For this reason, much effort is concentrated on the design of clean switching processes to optimize signal to noise ratios delivered at the output of the DAC. In this paper, we present a novel switch sizing and compensation technique for inverted R-2R ladder DACs. While traditional switch compensation in the ladder leads to very large switch devices steering MSBs currents, our method allows current-steering with reduced equally sized switches. Results of 12-b DAC test chips fabricated in a 0.18 µm process show that this new technique allows significant area savings, without impairing static accuracy. Other improvements brought by this technique include simplified switch driving circuitry and improved settling time.