SiSMA: a statistical simulator for mismatch analysis of MOS ICs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A 10-bit 200-MHz CMOS video DAC for HDTV applications
Analog Integrated Circuits and Signal Processing
Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing
Journal of Electronic Testing: Theory and Applications
An improved switch compensation technique for inverted R-2R ladder DACs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Quantization noise minimization in ΣΔ modulation based RF transmitter architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
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With the shrinking of device sizes, random device variations become a key factor limiting the performances of high-resolution complementary metal-oxide-semiconductor (CMOS) current-steering digital-to-analog converters (DACs). In this paper, we present a novel design methodology based on statistical modeling of MOS transistor drain current that allows designers to explore different DAC architectures and to study the effects of technological variations on system performance without using time-consuming Monte Carlo simulations. This technique requires as a first step the estimation of the mean value and the autocorrelation function of a single stochastic process. This stochastic process models the device drain current and summarizes all the random sources associated with the process/device variations since the current represents the effect of all of them. Subsequently, on the basis of such an approach, a behavioral model of current-steering DACs has been developed. Finally, the statistical simulation of static performances such as differential nonlinearity and integral nonlinearity has been carried out for different DAC architectures based on the behavioral model previously derived