An analysis of floating-point addition

Authors:
D. W. Sweeney
Affiliations:
-
Venue:
IBM Systems Journal
Year:
1965

Citing 0
Cited 7

Loss of Significance in Floating Point Subtraction and Addition

IEEE Transactions on Computers
The Burroughs Scientific Processor (BSP)

IEEE Transactions on Computers
Highlights of a Study of Floating-Point Instructions

IEEE Transactions on Computers
Analysis of Rounding Methods in Floating-Point Arithmetic

IEEE Transactions on Computers
A Survey of Some Recent Contributions to Computer Arithmetic

IEEE Transactions on Computers
Architecture of the IBM System/360

IBM Journal of Research and Development
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

Microelectronics Journal

Quantified Score

Hi-index	0.02

Visualization

Abstract

This paper analyzes the addition operation of floating-point systems. The analysis of a million executed floating-point additions is presented as an aid in optimizing design and measuring performance. The frequency of the various shifts for floating-point additions with different radices was derived from the basic data so that designs with various redices may be evaluated.