Complexity issues in VLSI: optimal layouts for the shuffle-exchange graph and other networks
Complexity issues in VLSI: optimal layouts for the shuffle-exchange graph and other networks
Enumerative combinatorics
The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
Work-preserving emulations of fixed-connection networks
STOC '89 Proceedings of the twenty-first annual ACM symposium on Theory of computing
Group action graphs and parallel architectures
SIAM Journal on Computing
ACM Transactions on Programming Languages and Systems (TOPLAS)
Theory of Information and Coding
Theory of Information and Coding
Distributed Ring Embedding in Faulty De Bruijn Networks
IEEE Transactions on Computers
Efficient Routing and Sorting Schemes for de Bruijn Networks
IEEE Transactions on Parallel and Distributed Systems
The Hyper-deBruijn Networks: Scalable Versatile Architecture
IEEE Transactions on Parallel and Distributed Systems
On a generalized model of labeled graphs
Discrete Applied Mathematics
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The deBruijn graph Bn is the state diagram for an n-stage binary shift register. It has 2n vertices and 2n + 1 edges. In this papers, it is shown that Bn can be built by appropriately “wiring together“ (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph, which is called a building block for Bn. The efficiency of such a building block is refined as the fraction of the edges of Bn which are present in the copies of the building block. It is then shown, among other things, that for any &agr; G which is a building block for Bn of efficiency &agr; for all sufficiently large n. These results are illustrated by describing how a special hierarchical family of building blocks has been used to construct a very large Viterbi decoder (whose floorplan is the graph B13) which will be used on NASA's Galileo mission.