Parallel Architecture for the Solution of Linear Equation Systems Implemented in FPGA

  • Authors:

  • Ruben Martinez Alonso;Domingo Torres Lucio

  • Affiliations:

  • -;-

  • Venue:
  • CERMA '09 Proceedings of the 2009 Electronics, Robotics and Automotive Mechanics Conference (cerma 2009)
  • Year:
  • 2009

  • Sorting networks on FPGA

    TELE-INFO'11/MINO'11/SIP'11 Proceedings of the 10th WSEAS international conference on Telecommunications and informatics and microelectronics, nanoelectronics, optoelectronics, and WSEAS international conference on Signal processing

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Abstract

This paper presents a parallel architecture for the solution of linear equations based on the Division Free Gaussian Elimination Method is presented.This architecture can handle single and double data that follows the IEEE standard 754 for floating-point data. Also, it can be implemented in a FPGA Spartan 3 of Xilinx. The mathematical algorithm is implemented in an array of processors. The main procedure inside each processor and the data distribution between processors is described. Furthermore, the synthesis of the designed modules for each processor that composed the proposed architecture is presented. The obtained algorithmic complexity is O(n^2) using a scheme of n^2 processors that perform the solution of the linear equations set.