A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT

  • Authors:

  • Jingbang Qiu;Tianci Huang;Takeshi Ikenaga

  • Affiliations:

  • -;-;-

  • Venue:
  • NCM '09 Proceedings of the 2009 Fifth International Joint Conference on INC, IMS and IDC
  • Year:
  • 2009

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Abstract

SIFT is regarded as one of the most robust feature point detection algorithms in CV field. The feature point detection part, allocating final positions of all feature points, majorly defines the accuracy and stability of the whole system. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing dual-pixel processing and the 3-stage-interpolation pipelined architecture with use of dual-port DDR2 memory access, we achieve to further improve process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 145.0 MHz, processing up to 40 VGA images including memory operations. Compared with conventional work, hardware cost is slightly increased as trade-off for accelerated speed. High efficiency as 98.72% and high cover rate as 92.85% are kept by our proposal. Our proposal is suitable as a real-time SIFT system structure.