Shape Indexing Using Approximate Nearest-Neighbour Search in High-Dimensional Spaces
CVPR '97 Proceedings of the 1997 Conference on Computer Vision and Pattern Recognition (CVPR '97)
Object Recognition from Local Scale-Invariant Features
ICCV '99 Proceedings of the International Conference on Computer Vision-Volume 2 - Volume 2
Scale & Affine Invariant Interest Point Detectors
International Journal of Computer Vision
Distinctive Image Features from Scale-Invariant Keypoints
International Journal of Computer Vision
A Performance Evaluation of Local Descriptors
IEEE Transactions on Pattern Analysis and Machine Intelligence
Digital Signal Processing
Hardware/Software co-design of a key point detector on FPGA
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Speeded-Up Robust Features (SURF)
Computer Vision and Image Understanding
A Parallel Hardware Architecture for Image Feature Detection
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
NCM '09 Proceedings of the 2009 Fifth International Joint Conference on INC, IMS and IDC
AdaBoost-based face detection for embedded systems
Computer Vision and Image Understanding
PCA-SIFT: a more distinctive representation for local image descriptors
CVPR'04 Proceedings of the 2004 IEEE computer society conference on Computer vision and pattern recognition
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Streaming Data Movement for Real-Time Image Analysis
Journal of Signal Processing Systems
ACCV'06 Proceedings of the 7th Asian conference on Computer Vision - Volume Part I
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology
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SIFT has shown a great success in various computer vision applications. However, its large computational complexity has been a challenge to most embedded implementations. This paper presents a low-cost embedded system based on a new architecture that successfully integrates FPGA and DSP. It optimizes the FPGA architecture for the feature detection step of SIFT to reduce the resource utilization, and optimizes the implementation of the feature description step using a high-performance DSP. Due to this novel design, this system can detect SIFT feature and extract SIFT descriptor for detected features in real-time. Extensive experiments demonstrate its effectiveness and efficiency.