A Parallel Hardware Architecture for Image Feature Detection

Authors:
Vanderlei Bonato;Eduardo Marques;George A. Constantinides
Affiliations:
Institute of Mathematical and Computing Sciences, The University of São Paulo, São Carlos, BR;Institute of Mathematical and Computing Sciences, The University of São Paulo, São Carlos, BR;Department of Electrical and Electronic Engineering, Imperial College London, London, UK
Venue:
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2008

Citing 6
Cited 1

A survey of CORDIC algorithms for FPGA based computers

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Shape Indexing Using Approximate Nearest-Neighbour Search in High-Dimensional Spaces

CVPR '97 Proceedings of the 1997 Conference on Computer Vision and Pattern Recognition (CVPR '97)
Obstacle avoidance and navigation in the real world by a seeing robot rover

Obstacle avoidance and navigation in the real world by a seeing robot rover
Scale & Affine Invariant Interest Point Detectors

International Journal of Computer Vision
Distinctive Image Features from Scale-Invariant Keypoints

International Journal of Computer Vision
Hardware/Software co-design of a key point detector on FPGA

FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

A real-time embedded architecture for SIFT

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for hardware implementation of the SIFT algorithm and proposes specific hardware optimizations considered fundamental to embed whole system on a single chip, which implements in parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.