Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video

  • Authors:

  • Kosuke Mizuno;Hiroki Noguchi;Guangji He;Yosuke Terachi;Tetsuya Kamino;Hiroshi Kawaguchi;Masahiko Yoshimoto

  • Affiliations:

  • -;-;-;-;-;-;-

  • Venue:
  • FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
  • Year:
  • 2010

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Abstract

This　paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution　video　(640 脳 480 pixels) at 56 frames per second (fps). 　Our proposed implementation made the operating frequency and memory bandwidth a half or less than that of the conventional FPGA implementation and as a result, we achieved a system that can provide low power consumption.