A parameterizable handel-C neural network implementation for FPGA

Authors:
C. Benbouchama;M. Tadjine;A. Bouridane
Affiliations:
E. M. P, Bordj El Bahri, Alger, Algérie;Ecole Nationale Polytechnique, El Harrach Alger, Algérie;School of Electronics, Electrical Engineering and Computer Science, Queen's University, Belfast
Venue:
HSI'09 Proceedings of the 2nd conference on Human System Interactions
Year:
2009

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Abstract

This paper shows the design possibility of a parameterizable implementation of neural multi-layer network on FPGA circuits (Field Programmable Gate Array) through the use of Handel-C language. The algorithm used for the training is the back-propagation. The tools of implementation and synthesis are the DK 4 of Celoxica and the ISE 6.3 of Xilinx. The targeted components are XCV2000 on Celoxica RC1000 board and XC2V1000 on RC200. The representation of the real numbers in fixed point was used for the data processing. The realization of the activation function is made with the approximate polynomial. A high level environment was designed in order to specify and introduce architecture parameters.