Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Modelling of through silicon via and devices electromagnetic coupling
Microelectronics Journal
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
Microelectronics Journal
Hi-index | 2.88 |
3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3@mm wide and 15@mm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible @p-shaped analytical parametrical model of the TSV.