Modelling of through silicon via and devices electromagnetic coupling

Authors:
Mohamed Abouelatta-Ebrahim;Rabah Dahmani;Olivier Valorge;Francis Calmon;Christian Gontrand
Affiliations:
Université de Lyon, INSA-Lyon, INL, CNRS-UMR5270, Villeurbanne F-69621, France;Université de Lyon, INSA-Lyon, INL, CNRS-UMR5270, Villeurbanne F-69621, France;Université de Lyon, INSA-Lyon, INL, CNRS-UMR5270, Villeurbanne F-69621, France and R3 Logic, 50 Chemin de l'Etoile, 38330 Montbonnot-Saint-Martin, France;Université de Lyon, INSA-Lyon, INL, CNRS-UMR5270, Villeurbanne F-69621, France;Université de Lyon, INSA-Lyon, INL, CNRS-UMR5270, Villeurbanne F-69621, France
Venue:
Microelectronics Journal
Year:
2011

Citing 3
Cited 1

Three-dimensional Integrated Circuit Design

Three-dimensional Integrated Circuit Design
RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

Microelectronic Engineering
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Microelectronics Journal

Transceiver with inductive coupling for wireless chip-to-chip communication using a 50-nm digital CMOS process

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper is essentially composed of two parts for future synthesis. We developed 2D and 3D simulations, starting from a 0.35@mm standard CMOS technology, focusing on through silicon via or redistribution layer induced coupling; nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter are investigated. We also study stacked devices in 3D circuits, in the radiofrequency range, and propagation of electromagnetic waves along some interconnections with discontinuities. This study is performed in the time domain-a finite-difference time-domain method is applied to the analysis of some vias flanked by two striplines, all embedded in silicon. Electric and magnetic field distributions, transmission and reflexion parameters, and pulse propagations along a transverse via are presented.