HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Exploiting Method-Level Parallelism in Single-Threaded Java Programs
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Exploiting reference idempotency to reduce speculative storage overflow
ACM Transactions on Programming Languages and Systems (TOPLAS)
Tight analysis of the performance potential of thread speculation using spec CPU 2006
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Exploitation of nested thread-level speculative parallelism on multi-core systems
Proceedings of the 7th ACM international conference on Computing frontiers
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Thread-level speculation (TLS) has been proposed as a means to parallelize difficult-to-analyze sequential codes. In this paper, we present a realistic measure of the performance potential of call-graph level TLS, using the SPEC CPU2006 benchmark suite and the Intel Core 2 Duo processor.