Exploitation of nested thread-level speculative parallelism on multi-core systems

Authors:
Arun Kejariwal;Milind Girkar;Xinmin Tian;Hideki Saito;Alexandru Nicolau;Alexander V. Veidenbaum;Utpal Banerjee;Constantine D. Polychronopoulos
Affiliations:
Yahoo! Inc., Sunnyvale, CA, USA;Intel Corporation;Intel Corporation;Intel Corporation;University of California at Irvine;University of California at Irvine;University of California at Irvine;University of Illinois at Urbana-Champaign
Venue:
Proceedings of the 7th ACM international conference on Computing frontiers
Year:
2010

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Abstract

Multi-cores such as the Intel Core 2 Duo, AMD Barcelona and IBM POWER6 are becoming ubiquitous. The number of cores and the resulting hardware parallelism is poised to increase rapidly in the foreseeable future. Nested thread-level speculative parallelization has been proposed as a means to exploit the hardware parallelism of such systems. In this paper, we present a methodology to gauge the efficacy of nested thread-level speculation with increasing level of nesting.