Waiting algorithms for synchronization in large-scale multiprocessors
ACM Transactions on Computer Systems (TOCS)
An architecture for mostly functional languages
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Modern Operating Systems
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
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A new hardware-based design is presented to support shared accesses in multi-core processors. In the proposed design, instructions updating shared variables are issued by the processor cores but executed by the proposed hardware unit that is snooping on the bus. After issuing such an instruction, the processor core can proceed immediately with subsequent instructions. The proposed hardware unit assumes the responsibility of buffering and sequentializing the multiple access requests from the processor cores. The proposed hardware is shown to be sequentially consistent for accesses to shared variables. Comparison against lock-based synchronization shows that the proposed hardware design can significantly reduce synchronization overheads.