Exploiting parallelism in a switch-level simulation machine

• Authors: E. H. Frank
• Venue: ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
• Year: 1986

The parallelism inherent in actual circuits suggests that this parallelism might be exploited in a switch-level simulation machine, in order to reduce total simulation time. This paper explores the extent to which this parallelism exists and the extent to which it can be exploited. The exploration is done in the context of a proposed multiprocessor simulation machine called the Fast-1. The Fast-1 is a form of data-flow machine in which switch-level circuits are represented as programs consisting of transistor and node instructions. In a multiprocessor Fast-1 these programs are partitioned onto one or more processors. Using a simulation of the Fast-1, experiments were performed using thirteen circuits, ranging in size from 78 to 20233 transistors. The most parallel circuit measured in these experiements potentially could be simulated almost 200 times faster on a multiprocessor than on a uniprocessor, assuming one instruction per processor and no-cost interprocessor communication. Using 64 processors, an atual speedup of 28 was achieved using contention-free interconnect, while a speedup of 12 was achieved when the 64 processors were connected by a broadcast bus for which they had to arbitrate.