Modular architecture for high performance implementation of FFT algorithm

  • Authors:

  • K. Sapiecha;R. Jarocki

  • Affiliations:

  • Technical University of Warsaw, Institute of Computer Science, 00-665 Warsaw, NowowieJska 15/19, Poland;Technical University of Warsaw, Institute of Computer Science, 00-665 Warsaw, NowowieJska 15/19, Poland

  • Venue:
  • ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
  • Year:
  • 1986

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Abstract

The paper presents two new versions of the FFT algorithm. Based on these versions a new VLSI oriented architecture for implementing of the FFT algorithm is introduced. It consists of a homogenous structure of processing elements. The structure has a performance equal to 1/tB transforms per second, where tB is the time needed for execution of a single butterfly computation.Besides high performance the architecture is modular and makes it possible to design a system which performs the DFT of any size with constant performance and without any extra circuitry. Moreover, the system can provide a built-in self test.