High-level optimization of integer multipliers over a finite bit-width with verification capabilities

Authors:
O. Sarbishei;M. Tabandeh;B. Alizadeh;M. Fujita
Affiliations:
Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran;Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran;VLSI Design and Education Center, University of Tokyo, CREST, Tokyo, Japan;VLSI Design and Education Center, University of Tokyo, CREST, Tokyo, Japan
Venue:
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Year:
2009

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Abstract

Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency compared to the conventional optimization approaches.