VLSI implementation of an edge-oriented image scaling processor

Authors:
Pei-Yin Chen;Chih-Yuan Lien;Chi-Pin Lu
Affiliations:
Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling processor. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture of our image scaling processor contains 10.4-K gate counts and yields a processing rate of about 200 MHz by using TSMC 0.18-µm technology.