Memory Efficient VLSI Architecture for QCIF to VGA Resolution Conversion
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
VLSI implementation of an edge-oriented image scaling processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Face detection system for SVGA source with hecto-scale frame rate on FPGA board
Microprocessors & Microsystems
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One of the most extended algorithms for image scaling is bicubic interpolation. In this paper a Hardware Architecture for Bicubic Interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicubic function to be used in HABI; the second one performs the interpolation process and the third one is a control unit that synchronizes the processing and the pipeline stages. The architecture work with monochromatic images, but it can extended for working with RGB color images. Our design description is coded in Handel-C language and implemented on a Xilinx Virtex II Pro FPGA. The proposed system runs 10 times faster than an Intel Pentium 4-based PC at 2.4 Ghz. Comparison with other related works are provided.