Parallel catastrophe modelling on a cell processor

  • Authors:

  • Frank Dehne;Glenn Hickey;Andrew Rau-Chaplin;Mark Byrne

  • Affiliations:

  • Carleton University, Ottawa, Canada;McGill University, Montreal, Canada;Flagstone Reinsurance, Halifax, Canada;Flagstone Reinsurance, Halifax, Canada

  • Venue:
  • CASCON '09 Proceedings of the 2009 Conference of the Center for Advanced Studies on Collaborative Research
  • Year:
  • 2009

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Abstract

In this paper we study the potential performance improvements for catastrophe modelling systems that can be achieved through parallelization on a Cell Processor. We studied and parallelized a critical section of catastrophe modelling, the so called "inner loop", and implemented it on a Cell Processor running on a regular Playstation 3 platform. The Cell Processor is known to be a challenging environment for software development. In particular, the small internal storage available at each SPE of the Cell Processor is a considerable challenge for catastrophe modelling because the catastrophe modelling algorithm requires frequent accesses to large lookup tables. Our parallel solution is a combination of multiple techniques: streaming data to the SPEs and parallelizing inner loop computations, building caches on the SPEs to store parts of the large catastrophe modelling lookup tables, vectorizing the computation on the SPEs, and double-buffering the file I/O. On a (Playstation 3) Cell Processor with six active SPEs and 4-way vectorization on each SPE (implying a maximum theoretical 24x speedup), we were able to measure a sustained 16x speedup for our parallel catastrophe modelling code over a wide range of data sizes for real life Japanese earthquake data.