A Study of Side-Channel Effects in Reliability-Enhancing Techniques

  • Authors:
  • Jianwei Dai;Lei Wang

  • Affiliations:
  • -;-

  • Venue:
  • DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

Reliability-enhancing techniques are critical for nanoscale integrated systems under the pressure of various physical non-idealities such as process variations and manufacturing defects. However, it is unclear how these techniques will affect the side-channel information leaked through hardware implementations. The related side-channel effects may have direct implications to the security requirement in a wide range of applications. In this paper, we investigate this new problem for trusted hardware design. Employing information-theoretic measures, the relationship between reliability enhancements and the induced side-channel effects is quantitatively evaluated. Simulation results on EDC/ECC schemes in memory circuits are presented to demonstrate the application of the proposed method.