Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Dynamic power management for multidomain system-on-chip platforms: An optimal control approach
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. For power reduction, multiple voltage-frequency levels are successfully applied to 2-D NoCs, but never with a generic approach to 3-D counterparts; in which low heat conductivity of insulator layers makes high dense temperature distribution at layers away from heat sink. In this paper, a thermal-aware methodology for regular 3-D NoCs based on multiple voltage levels is proposed. Given an application task graph, this methodology determines an efficient mapping of tasks onto network tiles, considering inherent computation and communication requirements of the tasks and thermal resistance from any silicon layer to the ambient. Then, a heuristic approach is utilized to determine voltage and frequency specifications of all IP cores, such that total power is reduced, dissipated heat is properly conducted to the layers close to the heat sink, and application requirements (in terms of deadline) are satisfied. The experiments confirm a significant saving in total power while performance of the running application is guaranteed.