An analytical model to exploit memory task scheduling

  • Authors:

  • Hsiang-Yun Cheng;Jian Li;Chia-Lin Yang

  • Affiliations:

  • National Taiwan University, Taipei, Taiwan, R.O.C. and IBM Austin Research Laboratory, Austin, TX;IBM Austin Research Laboratory, Austin, TX;National Taiwan University, Taipei, Taiwan, R.O.C.

  • Venue:
  • Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
  • Year:
  • 2010

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Abstract

Memory Wall has been a well-known obstacle to processor performance improvement. The dawn of many-core processors will further exaggerate the problem. As a result, efficient memory task scheduling has been one important means to sustaining the performance growth. In this paper, we first develop an analytical model to capture the essence of on-chip compute and off-chip communication as shown in the stream programming model. It estimates the potential speedup that can be achieved by restricting the number of simultaneous memory tasks to reduce memory bandwidth contention. We then corroborate the analytical model with experimental results from task scheduling on real hardware. Correlation between the analytical and experimental results offers both insight into the benchmarks running on the hardware and opportunities to extend the analytical model. Our results show that restricting the number of simultaneous memory tasks achieves up to 60% performance improvement with a pool of synthetic workloads.