Computer Vision, Graphics, and Image Processing
The cytocomputer: A practical pipelined image processor
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Image Analysis and Mathematical Morphology
Image Analysis and Mathematical Morphology
SILK: a simulated evolution router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Systolic routing hardware: performance evaluation and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Class of Cellular Architectures to Support Physical Design Automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Detailed Router Based on Incremental Routing Modifications: Mighty
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Survey of Hardware Accelerators Used in Computer-Aided Design
IEEE Design & Test
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Many scientific and technical applications require high-performance, low-cost architectures. Systolic array processors are good examples of these machines. In this paper a systolic architecture with S stages and p processors per stage is proposed. A performance analysis shows the merits of this architecture. Applications in the image processing and circuit layout fields are also presented.